This application relies for priority upon Korean Patent Application No. 2001-81319, filed on Dec. 19, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to semiconductor devices and methods for fabricating the same and, more particularly, to semiconductor devices including nonvolatile memory transistors, resistors, and mask ROMs (MROMs) and methods for fabricating the same.
Like identification cards, credit cards, and electronic cash, applications of smart cards having multiple functions have been on the increase. Smart cards not only store data of users and transactions, but also include programs adequate for inherent functionality. Smart cards therefore comprise semiconductor devices having both nonvolatile memory transistors for recording and storing data and MROMs for storing program data. In addition, the semiconductor devices used in the smart cards further include resistors for effecting their operation.
A nonvolatile memory transistor employed in a smart card is preferably an electrically erasable programmable read-only memory (EEPROM) of a floating gate tunnel oxide (FLOTOX) type (hereinafter inclusively referred to as a FLOTOX-type EEPROM), which offers a stable characteristic of data storage. In addition, the resistor preferably comprises a junction region formed in a semiconductor substrate, i.e., a junction resistor, so as to have an appropriate resistance value. Meanwhile, to store binary data (i.e., xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d), the MROM device employs a depletion-mode MOSFET or an enhancement-mode MOSFET.
FIG. 1 is a cross-sectional view of a typical FLOTOX-type EEPROM.
Referring to FIG. 1, a device isolation layer 15 is disposed at a predetermined region of a semiconductor substrate 10 to define an active region. A memory gate 50 and a select gate 51 are disposed to cross over the active region and the device isolation layer 15. A gate oxide layer 30 is intervened between the memory gate 50 and the active region and between the select gate 51 and the active region. A tunnel oxide layer 35, which is surrounded by the gate oxide layer 30, is disposed between the active region and the memory gate 50. The thickness of the tunnel oxide layer is less than that of the gate oxide layer 30.
Generally, the memory gate 50 and the select gate 51 are disposed in parallel with each other. The memory gate 50 includes a floating gate 40, a gate interlayer insulation layer 41, and a control gate 42. The floating gate 40 covers an entire top surface of the tunnel oxide layer 35. Also, the select gate 51 includes a lower select gate 43, a select gate interlayer insulation layer 44, and an upper select gate 45.
A floating junction region 20, of which conductivity type is different from that of the semiconductor substrate 10, is disposed in the active region under the tunnel oxide layer 35. The floating junction region 20 extends through the active region between the memory gate 50 and the select gate 51. A source/drain junction region 60 is disposed in the active region about the select gate 51 and the memory gate 50.
FIG. 2 is a cross-sectional view of a typical resistor of a semiconductor device.
Referring to FIG. 2, a device isolation layer 15 is disposed at a predetermined region of a semiconductor substrate 10 to define an active region. A gate oxide layer 30 is disposed on the active region. A resistive junction region 70 including impurities having a conductivity type that is different from that of the semiconductor substrate 10, is disposed in the active region. Also, resistor-connecting terminals 75 are disposed at both edges of the resistive junction region 70 such that they penetrate the gate oxide layer 30 to connect to the resistive junction region 70.
To use the resistive junction region 70 as a semiconductor device resistor, the sheet resistance of the resistive junction region 70 preferably ranges from 500 to 1000 ohm per square. Meanwhile, since a conductive material, for example, a polysilicon material including impurities, has a sheet resistance of about 10 ohm per square, in case of using the conductive material for the resistive junction region, resistance patterns should be formed in excessively long patterns.
The resistance of the resistive junction region 70 is determined by the concentration of impurities included therein. Accordingly, to maintain a precise resistance, it is necessary to control the amount and species of the impurities being doped into the resistive junction region 70. However, according to conventional approaches, a gate pattern or the like, which may serve as a mask for the ion implantation process, is not formed on the resistive junction region 70. As a result, the resistive junction region 70 may be exposed during subsequent ion implantation processes, leading to loss of control over providing the desired resistance in the resistive junction region 70.
FIG. 3 is a cross-sectional view of a typical MROM transistor.
Referring to FIG. 3, a device isolation layer is disposed at a predetermined region of a semiconductor substrate 10 to define an active region. An MROM gate oxide layer 35 is disposed on the active region. On the MROM gate oxide layer 35, MROM gate patterns 47 are disposed to cross the active region and the device isolation layer. An MROM junction region 62 having impurities of a conductivity type that is different from that of the semiconductor substrate 10, is disposed in the active region between the MROM gate patterns 47. The MROM junction region 62 serves as a source/drain region of the MROM transistor.
A channel junction region 80, which is in contact with the MROM junction region 62, may be additionally disposed in the active region under the MROM gate pattern 47. A depletion mode MOSFET includes the channel junction region 80, while an enhancement mode MOSFET does not include the channel junction region 80. Here, the channel junction region 80 includes impurities having a conductivity type that is the same as that of the MROM junction region 62. Thus, when the gate bias is 0V, the depletion mode MOSFET is already in a turn-on state.
As described above, semiconductor devices used in smart cards include the EEPROMs, the resistors, and the MROMs. To reduce fabrication costs, it is desired to simplify the process for fabricating the EEPROMs, resistors, and MROMs for such devices.
It is therefore a feature of the present invention to provide semiconductor devices including nonvolatile memory transistors, resistors, and mask ROMs (MROMs).
It is another feature of the present invention to provide methods for fabricating semiconductor devices including nonvolatile memory transistors, resistors, and MROMs.
In accordance with broad aspects of the present invention, provided is a semiconductor device including a resistor having a covering gate as well as a resistive junction region and a channel junction region, of which depths are the same as that of a floating junction region. The semiconductor device comprises a device isolation layer that is formed at a predetermined region of a semiconductor substrate to define a cell active region, a resistor active region, and an MROM active region. The semiconductor device further comprises the floating junction region, the resistive junction region, and the channel junction region, which are formed in the cell active region, the resistor active region, and the MROM active region, respectively. The floating junction region, the resistive junction region, and the channel junction region are formed to the same depth. Also, the covering gate and an MROM gate are disposed to cross over the resistor active region, and the MROM active region, respectively. A memory gate and a select gate are disposed to cross over the cell active region.
Preferably, a first gate oxide layer is disposed under the covering gate, the select gate, and the memory gate. A tunnel oxide layer, which is surrounded by the first gate oxide layer, is preferably disposed under the memory gate. At this time, a thickness of the tunnel oxide layer is less than that of the first gate oxide layer. Also, a second gate oxide layer, which is thinner than the first gate oxide layer, is preferably disposed under the MROM gate.
The memory gate includes a floating gate, a gate interlayer insulation layer, and a control gate, which are sequentially stacked. The select gate includes a lower select gate, a select gate interlayer insulation layer, and an upper select gate, which are sequentially stacked. In this case, layers constituting the select gate are preferably composed of the same materials as layers constituting the memory gate. It is also preferable that the covering gate is composed of the same material layer as the select gate, and the MROM gate is composed of the same material layer as the control gate.
The floating junction region, the resistive junction region, and the channel junction region include the same impurities of the same impurity concentration.
The present invention also provides a method for fabricating a semiconductor device, which comprises forming junction regions for various purposes through a one-time ion implantation process. The method includes forming a device isolation layer at a predetermined region of a semiconductor substrate to define a cell active region, a resistor active region, and an MROM active region. A first ion implantation process is then performed, thereby forming a floating junction region, a resistive junction region, and a channel junction region in the cell active region, the resistor active region, and the MROM active region, respectively. Thereafter, a select gate, a memory gate, and a covering gate are formed on the cell active region, the resistor active region, and the MROM active region, respectively, where the first ion implantation process is implemented.
Preferably, a first gate oxide layer is formed on the cell active region, the resistor active region, and the MROM active region, before or after the first ion implantation process. Meanwhile, the first ion implantation process is implemented using impurities having a conductivity type that is different from that of the cell active region, the resistor active region and the MROM active region.
After forming the first gate oxide layer, it is preferable to additionally form a tunnel oxide layer, which is thinner than the first gate oxide layer.
The formation of the gates preferably comprises forming a first conductive layer, a first insulation layer, and a second conductive layer, which are sequentially stacked, on an entire surface of a semiconductor substrate where the first ion implantation process is implemented, then successively patterning the second conductive layer, the first insulation layer, and the first conductive layer.
In the meantime, the first conductive layer is preferably patterned at the cell active region before forming the first insulation layer, thereby forming a first conductive layer pattern having an opening, which is parallel to the cell active region.
Before forming the second conductive layer, preferably, the first conductive layer and the first insulation layer are patterned to expose a top surface of the MROM active region and a second gate oxide layer is then formed on the exposed MROM active region.
It is preferable that the floating junction region, the resistive junction region, and the channel junction region are formed at the same time.